GB/T 46280.5-2025
ActiveSpecification for chiplet inerconnection interface—Part 5: Physical layer technical requirements based on 2.5D package
芯粒互联接口规范 第5部分：基于2.5D封装的物理层技术要求
Application Summary AI generated
This standard specifies the physical layer technical requirements for chiplet interconnection interfaces using 2.5D packaging, including electrical parameters, signal integrity, and timing specifications. It is applied in the design and manufacturing of advanced semiconductor packages, such as high-performance computing, AI accelerators, and data center processors, where multiple chiplets are integrated on an interposer. The standard ensures interoperability and reliable data transmission between chiplets from different suppliers in multi-die system-in-package (SiP) designs.
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