GB/T 46280.4-2025
ActiveSpecification for chiplet inerconnection interface—Part 4: Physical layer technical requirements based on 2D package
芯粒互联接口规范 第4部分：基于2D封装的物理层技术要求
Application Summary AI generated
This standard specifies the physical layer technical requirements for chiplet interconnection interfaces within a 2D package, including electrical parameters, signal integrity, and timing specifications. It is applied in the design and manufacturing of multi-die integrated circuits, such as high-performance computing processors and advanced system-in-package (SiP) modules, where chiplets are placed side-by-side on a substrate. The standard ensures interoperability and reliable data transmission between chiplets from different suppliers in 2D packaging configurations.
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