GB/T 44796-2024

Active

Integrated circuit 3D packaging—Requirement for bumping-wafer-sawing process and evaluation

集成电路三维封装 带凸点圆片划片工艺过程和评价要求

Standard Type
GBT
ICS
31.200
CCS
L55
Status
Active
Issue Date
2024-10-26
Implementation
2025-05-01
Centralized Committee
工业和信息化部(电子)
Issuing Authority
国家市场监督管理总局、国家标准化管理委员会

Application Summary AI generated

This standard specifies the process requirements and evaluation methods for the wafer sawing of bumped wafers used in 3D integrated circuit packaging. It is applied in semiconductor manufacturing facilities to ensure the quality and reliability of singulated dies with bumps, particularly for advanced packaging technologies like fan-out wafer-level packaging and through-silicon via (TSV) integration. The standard provides guidelines for process control, defect inspection, and mechanical integrity assessment during the dicing of bumped wafers.

Related Standards

Transparency note: The application summary and key sentences on this page were automatically generated by AI from the standard's original text. This content has not been human-verified and should not be used for compliance or regulatory purposes. Always refer to the official standard document from the issuing authority.