GB/T 44775-2024
ActiveIntegrated circuit 3D packaging— Requirement for die stack process and evaluation
集成电路三维封装 芯片叠层工艺过程和评价要求
Application Summary AI generated
This standard specifies the process requirements and evaluation methods for die stacking in 3D integrated circuit packaging. It is applied in the semiconductor manufacturing industry to guide the assembly, quality control, and reliability testing of vertically stacked chips in advanced packaging, such as memory, logic, and heterogeneous integration products.
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