GB/T 43536.2-2023
ActiveThree dimensional integrated circuits—Part 2：Alignment of stacked dies having fine pitch interconnect
三维集成电路 第2部分：微间距叠层芯片的校准要求
Application Summary AI generated
This standard specifies the alignment requirements for stacked dies with fine pitch interconnects in three-dimensional integrated circuits (3D ICs). It is applied in semiconductor manufacturing and packaging to ensure precise vertical stacking and electrical connectivity between thin chips. The standard is critical for high-density, high-performance electronics like advanced processors, memory stacks, and image sensors.
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