GB/T 36474-2018

Active

Semiconductor integrated circuit—Measuring methods for double data rate 3 synchronous dynamic random access memory(DDR3 SDRAM)

半导体集成电路 第三代双倍数据速率同步动态随机存储器 (DDR3 SDRAM)测试方法

Standard Type
GBT
ICS
31.200
CCS
L56
Status
Active
Issue Date
2018-06-07
Implementation
2019-01-01
Centralized Committee
工业和信息化部(电子)
Issuing Authority
国家市场监督管理总局、中国国家标准化管理委员会

Application Summary AI generated

This standard specifies the electrical parameters, timing characteristics, and functional test methods for DDR3 SDRAM devices. It is applied in the semiconductor industry for design verification, production testing, and quality assurance of DDR3 memory chips used in computers, servers, and embedded systems. The standard ensures consistent performance evaluation across manufacturers and compatibility testing for system integration.

Related Standards

Transparency note: The application summary and key sentences on this page were automatically generated by AI from the standard's original text. This content has not been human-verified and should not be used for compliance or regulatory purposes. Always refer to the official standard document from the issuing authority.