GB/T 35010.5-2018
ActiveSemiconductor die products—Part 5：Requirements for concerning electrical simulation
半导体芯片产品 第5部分：电学仿真要求
Application Summary AI generated
This standard specifies the requirements for electrical simulation models of semiconductor die products, including model accuracy, validation procedures, and data format. It is applied in the design and verification phases of integrated circuit development, ensuring that simulation models accurately represent the electrical behavior of bare dies for system-level integration. The standard is used by semiconductor manufacturers, design houses, and electronic design automation (EDA) tool vendors to facilitate reliable pre-production testing and compatibility in multi-chip modules or system-in-package applications.
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Transparency note: The application summary and key sentences on this page were automatically generated by AI from the standard's original text. This content has not been human-verified and should not be used for compliance or regulatory purposes. Always refer to the official standard document from the issuing authority.